1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device for burying a recess, particularly to a manufacturing method for a semiconductor device capable of easily and efficiently burying plural recesses having different aspect ratios.
2. Description of the Related Art
Recently, in a process of forming a dielectric film in a recess portion such as an shallow isolation trench among processes of manufacturing the semiconductor device, as a finer-line process and a higher-level of integration develop in an element and an interconnect, use of high-density plasma VD (HDP-CVD) method being common. However, with further development of the finer-line process and higher-level of integration, even if the HDP-CVD method is used, there is easily generated a problem that a frontage (opening) is closed to generate a void inside the trench before the inside of the trench is filled with the dielectric film. That is, even with the HDP-CVD method, a property of filling the fine trench is approaching a limit. Therefore, there is demanded a dielectric film forming technique having the excellent trench filling property which can deal with the trench having the higher aspect ratio (trench depth/opening width).
A coating film can be cited as an example of the film having the excellent trench filling property. However, in the coating film, cracking and peeling off easily occur, and a device property is possibly degraded by a fixed charge. In order to prevent the problems that may arise, a space pattern having a wider area in a line and space pattern, where the volume of the coating film is increased, is removed by etching. However, in order to perform the etching, it is necessary that a lithography process be newly added to cover the narrow pitch region such as the memory cell portion with a resist film or another dielectric film, which possibly results in cost increase.
There is a so-called condensation CVD method as the film forming method having the excellent trench filling property. For example, a technique of using the condensation CVD is disclosed in “Novel shallow trench isolation process using flowable oxide CVD for sub-100-nm DRAM”, Sung-Woong, et al., 9.4.1-9.4.4, IEDM 233-236, 2002 IEEE. However, there is a problem that the film formed by the condensation CVD method is inferior to the film formed by the HDP-CVD method in a crack-resistant property. For example, the dielectric film is deposited by the condensation CVD method until a thickness required in a device design stage is obtained. Or, the dielectric film is deposited by the condensation CVD method until the thickness required in a manufacturing process allowing a margin in polishing of post-forming is obtained. Then, there is a risk of cracking in the dielectric film. Particularly, the risk of cracking in the dielectric film is increased when the dielectric film formed by the condensation CVD method is exposed to a high temperature in the process of manufacturing a transistor periphery.